1. Field of the Invention
The present invention relates to a latch circuit for cyclically latching input signals and, more particularly, to a dynamic latch circuit to be formed within an LSI circuit chip.
2. Description of the Related Art
An LSI circuit chip is known which contains the dynamic latch circuit shown in FIG. 1. This latch circuit comprises an input terminal D, an output terminal OUT, CMOS clocked inverters C1 and C2, and a CMOS inverter IV. Clocked inverters C1, C2, and CMOS inverter IV are connected in cascade between input terminal D and output terminal OUT, with inverters C1 and C2 forming a master/slave register, and CMOS inverter IV functioning as an output buffer. The output operation of either CMOS clocked inverter is controlled by a pair of control clock signals .phi. and .phi. which are complementary in potential and generated at a predetermined frequency.
Clocked inverter C2 charges or discharges the parasitic capacitance of node B of clocked inverter C2 and CMOS inverter IV during the first period, from the leading edge to the trailing edge of control clock pulses .phi. and .phi., outputting a high impedance, from the trailing edge to the leading edge thereof, during the second period. Conversely, clocked inverter C1 outputs a high impedance during the first period of control clock pulses .phi. and .phi., and, during the second period thereof, generates an output voltage, to charge or discharge the parasitic capacitance of node A of inverters C1 and C2. The potential of node A is used as the input signal to clocked inverter C2, and remains substantially equal to the output voltage of inverter C1 during the first period, due to the parasitic capacitance of node A. The potential of node B, on the other hand, is used as the input signal to CMOS inverter IV, remaining substantially equal to the output voltage of inverter IV during the second period, due to the parasitic capacitance of node B. Hence, the latch circuit latches the voltage signal supplied to input terminal D in one cycle, and, in the next cycle, outputs a logic signal "H" or "L", corresponding to the latched signal, from output terminal OUT.
When the LSI circuit is subjected to a DC test, a latch-up test, or other similar tests, wherein the latch circuit is not required to latch input signals cyclically, control clock pulses .phi. and .phi. are not supplied inverters C1 and C2 for an extended period of time. After the supply of clock pulses .phi. and .phi. has been stopped, and their levels set respectively at "L" and "H", the potential of node B gradually changes toward a value midway between the potential of the power-supply terminal VSS and that of the power-supply terminal VDD, this being due to a leakage current or the like. When the potential of node B changes to the extent that it can no longer produce a logic signal representing the output voltage of clocked inverter C2, both the P-channel and N-channel transistors forming inverter IV are turned on, whereby a short-circuit current starts flowing continuously between the power-supply terminals VDD and VSS. Since, in order for inverter IV to function as the output buffer, its MOS transistors have dimensions greater than those of the MOS transistors which form the master/slave register, the short-circuit current will therefore be relatively large, with the result that the difference between the potential of power-supply terminal VDD and that of power-supply terminal VSS will very likely be reduced. Such a reduction in the potential difference will cause the LSI circuit to operate erroneously, and hence decrease the reliability of the test. Further, if the LSI circuit happens to contain a large number of dynamic latch circuits, the sum of the short-circuit currents flowing in these circuits may exceed the rated current which can flow in the LSI circuit, in which case, the LSI circuit will break down.